We've just heard that Apple is evaluating all 3rd party RAM upgrades for the PowerBook due to reports of problems with some designs currently on the market. While we are not sure what the outcome of this will be, we wanted to pass along what we know so that folks could look carefully at 3rd party RAM offerings and also check out whether any difficulties they are having with their PB's might be linked to RAM upgrades they've installed.
Our engineering team outlined the issues for me as the following:
1- TSOP v. SOP: The PB's space for RAM upgrades is situated between the logic board and the keyboard area of the case. The space available is pretty narrow. TSOP (Thin Small Outline Package) components ensure a thin board that floats between the kb and the logic board. This allows for enough air flow and avoids stresses when certain keys are typed. With SOP designs, the risk of damage from excessive heat (little or no air flow and/or contact between RAM components and case or logic board) and the jarring when keys hit the components risk a variety of problems including damage to the RAM connections and board failure.
2- Apple specs for RAM upgrades call for rigid board designs. The reasoning is that the jolting and the delicate location the RAM slots in the PB make flexible boards unreliable.
3- Some vendors are selling DRAM rather than psuedostatic - there's been a lot of talk about that here already. Apple specs call for pseudostatic with good reason. DRAM draws more power which may shorten battery life and also generates greater heat which may compromise the thermal design of the PB CPU. (BTW, true Static RAM does not seem viable for the PB right now -- apparently it would be too expensive to justify a very minor increase in battery life - estimated at less than 15 minutes even if the Static RAM increased battery life a full 100% which it would not.)
That's the news as I have it so far ... we're suggesting folks look for PB RAM upgrades that are as close to Apple's specs as possible since those specs take into consideration the overall implications of RAM designs for PB performance.
